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NJW1109
Headphone Amplifier with Electronic Volume
s GENERAL DESCRIPTION The NJW1109 is a headphone amplifier with electronic volume. It includes widely gain adjustable volume, +20 to -80 dB, and mute 2 function. These are controlled by I C bus. The NJW1109 is suitable for headphone output on TV set. s PACKAGE OUTLINE
NJW1109D
NJW1109M
NJW1109V
s FEATURES q Operating Voltage q Electronic Volume 2 q I C Bus Interface q Bi-CMOS Technology q Package Outline s BLOCK DIAGRAM
7.5 to 10 V +20dB to -80dB / 0.5dB step, Mute DIP14, DMP14, SSOP14
CAPa
SDA SCL
IC Interface
2
ADR OUTa
IN a
VOL
IN b
VOL
OUTb
Bias
Vref
CAPb s PIN FUNCTION
No. 1 1 14 2 3 4 5 7 8 6 7
SYMBOL
V+ GND
V+ OUTb N.C. CAPb INb ADR SDA
FUNCTION Power Supply Bch Output No Connect Balance control click noise absorbing capacitor connect terminal Bch Input I2C Bus Slave Address Select I2C Bus Data Input
No. 8 9 10 11 12 13 14
SYMBOL
SCL Vref INa CAPa N.C. OUTa GND
FUNCTION I2C Bus Clock Input Reference voltage stabilized capacitor connect terminal Ach Input Volume control click noise absorbing capacitor connect terminal No Connect Ach Output Ground
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NJW1109
s ABSOLUTE MAXIMUM RATING (Ta=25C) PARAMETER SYMBOL Supply Voltage Power Dissipation Operating Temperature Range Storage Temperature Range V
+
RATING 12 500 (DIP14) 500* (DMP14) 440* (SSOP14) -20 to +75 -40 to +125
UNIT V mW C C
PD Topr Tstg
*(Note) EIA/JEDEC STANDARD Test board(76.2 x 114.3 x 1.6mm, 2layers, FR-4)mounting
s ELECTRICAL CHARACTERISTICS
(V =9V, VIN=-20dBV, f=1kHz, RL=100, VOL = 0dB , Ta=25C) qPOWER SUPPLY
+
PARAMETER Operating Voltage Operating Current Reference Voltage
qAMPLIFIER
SYMBOL V
+
TEST CONDITION No Signal
MIN. 7.5 4.0
TYP. 9 5
4.5
MAX. 10 8
5.0
UNIT V mA
V
ICC VREF SYMBOL GVMAX GVMIN Gv VIM PO THD CS Mute VNO1 VNO2 PSRR SYMBOL
VADRH VADRL
PARAMETER Volume Maximum Gain Volume Minimum Gain Voltage Gain Channel Balance Maximum Input Voltage Output Power Total Harmonic Distortion Channel Separation Mute Level Output Noise Voltage 1 Output Noise Voltage 2 Power Supply Ripple Rejection
qCONTROL
TEST CONDITION
VOL = +20dB setting VOL = -80dB setting VOL = 0dB setting VOL = -10dB setting
MIN. 18 -1.5 8.9 (2.8) 70 70 MIN. V /2 +
TYP. 20 -80 0 9.5 (3.0) 100 0.1 80 -100 -95 (18) -105 (5.6) 70 TYP. -
MAX. 22 1.5 1 -90 -85 (56) -95 (18) MAX. 1.0
UNIT dB dB dBV (Vrms) mW % dB dB dBV
(Vrms)
THD=3%
VOL = 10dB, THD=10% VOL = 0dB setting
Rg=600, Vin = 0dBV
VOL = Mute, Vin = 0dBV
Rg=0, A-Weighted
VOL = Mute
dBV
(Vrms)
Rg=0, A-Weighted Vripple=-20dBV, Rg=0
dB UNIT V V
PARAMETER
High Level Input Voltage Low Level Input Voltage
TEST CONDITION
High : Slave Address 84H Low : Slave Address 80H
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NJW1109
s I C BUS CHARACTERISTICS
2
2
(SDA, SCL) SYMBOL VIL VIH Vhys VOL tof tSP Ii Ci fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tr tf tSU:STO tBUF Cb VnL VnH MIN. 0.0 2.5 0.25 0
20+0.1Cb
I C BUS Load Conditions: Pull up resistance 4k (Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER Low Level Input Voltage High Level Input Voltage Hysteresis of Schmitt trigger inputs LOW level output voltage (3mA at SDA pin)
Output fall time from VIHmin to VILmax with a bus capacitance from 10pF to 400pF Pulse width of spikes which must be suppressed by the input filter
TYP. -
MAX. 1.5 5.0 0.4 250 50 10 10 400 0.9 300 300 400 -
UNIT V V V V ns ns A pF kHz s s s s s ns ns ns s s pF V V
0 -10 0.6 1.3 0.6 0.6 0 100 0.6 1.3 0.5 1
Input current each I/O pin with an input voltage between 0.1VDD and 0.9VDDmax
Capacitance for each I/O pin SCL clock frequency Hold time (repeated) START condition. LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Noise margin at the LOW level Noise margin at the HIGH level
Cb ; total capacitance of one bus line in pF.
SDA
tf
tr
tSU:DAT
tf
tHD:STA
tSP
tr
tBUF
SCL
tHD:STA S tLOW tHD:DAT tHIGH
tSU:STA Sr
tSU:STO P S
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NJW1109
sTERMINAL DESCRIPTION No. SYMBOL FUNCTION EQUIVALENT CIRCUIT VOLTAGE
17k
5 10
INb INa
Bch Input V+/2 Ach Input
2 13
OUTb OUTa
Bch Output V+/2 Ach Output
12k
4
CAPb
Balance control click noise absorbing capacitor connect terminal
8k
3.8V
11
CAPa
Volume control click noise absorbing capacitor connect terminal
8k
3.1V
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NJW1109
sTERMINAL DESCRIPTION No. SYMBOL FUNCTION EQUIVALENT CIRCUIT VOLTAGE
4k
6
ADR
I C Bus Slave Address Select
12k
2
-
7 8
SDA SCL
I C Bus Data Input I C Bus Clock Input
12k
2
2
4k
-
200k
1.3k
9
Vref
Reference voltage stabilized capacitor connect terminal
200k
V+/2
1
V+
Power Supply
-
-
14
GND
Ground
-
-
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NJW1109
s TEST CIRCUIT TEST CIRCUIT
1 (GVMAX, GVMIN, Gv, VIM, PO, THD, Mute)
Input B Output B
VADRL VADRH 0.47F 1F
100 100F
BPF:400Hz to 30KHz
V+
7 SDA
6 ADR
5 INb
4 CAPb
3 NC
2 OUTb
1 V+
10F
VOL I C Bus Interface VOL Bias
2
SCL 8
Vref 9
10F
INa 10
CAPa 11
NC 12
OUTa GND 13
100F
14
0.47F 1F 100
Output A
Input A
BPF:400Hz to 30KHz
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NJW1109
TEST CIRCUIT
2 (Icc, VREF, VNO1,VNO2)
Input B
Output B
VADRL VADRH 0.47F 1F
100 100F
A-Weighted
V+
[Icc]
7 SDA
6 ADR
5 INb
4 CAPb
3 NC
2 OUTb
1 V+
10F
VOL I C Bus Interface VOL Bias
2
SCL 8
Vref 9
INa 10
CAPa 11
NC 12
OUTa GND 13
100F
14
[VREF] 10F 0.47F 1F
Output A
100
Input A
A-Weighted
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NJW1109
TEST CIRCUIT
3 (CS)
Input B
Rg=600 VADRL VADRH
Output B
100 100F 1F BPF:400Hz to 30KHz
V+
0.47F
7 SDA
6 ADR
5 INb
4 CAPb
3 NC
2 OUTb
1 V+
10F
VOL
Rg=600
I C Bus Interface VOL Bias
2
SCL 8
Vref 9
INa 10
CAPa 11
NC 12
OUTa GND 13 14
0.47F 10F 1F
100F
Output A
BPF:400Hz to 30KHz
Rg=600
Input A
100
-8-
NJW1109
TEST CIRCUIT
4 (PSRR)
Input B Output B
100 100F 1F BPF:400Hz to 30KHz
VADRL VADRH
Rg=0
0.47F
7 SDA
6 ADR
5 INb
4 CAPb
3 NC
2 OUTb
1 V+
10F
V+
VOL I C Bus Interface VOL Bias
2
SCL 8
Vref 9
INa 10
CAPa 11
NC 12
OUTa GND 13
100F
14
0.47F 10F Rg=0 1F
Output A
BPF:400Hz to 30KHz
100
Input A
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NJW1109
s APPLICATION CIRCUIT
Input B
30 30
Output B
0.47F 1F
100F
V+
7 SDA
6 ADR
5 INb
4 CAPb
3 NC
2 OUTb
1 V+
10F
VOL I C Bus Interface VOL Bias
2
SCL 8
Vref 9
10F
INa 10
CAPa 11
NC 12
OUTa GND 13
100F
14
0.47F 30 1F 30
Output A
Input A Mute
Mute
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NJW1109
s DEFINITION OF I C REGISTER q I C BUS FORMAT
MSB LSB MSB LSB MSB LSB
2 2
S
1bit
Slave Address
8bit
A
1bit
Select Address
8bit
A
1bit
Data
8bit
A
P
1bit 1bit
S: Starting Term A: Acknowledge Bit P: Ending Term q SLAVE ADDRESS
MSB LSB
1 1
0 0
0 0
0 0
0 0
0 1
0 0
0 0
80H (ADR = Low) 84H (ADR = High)
q SELECT ADDRESS
The auto-increment function cycles the select address as follows. 00H01H00H Select Address 00H 01H CHS BAL BIT D7 D6 D5 D4 VOL Don't Care D3 D2 D1 D0
!CONTROL REGISTER DEFAULT VALUE Control register default value is all "0".
Select Address 00H 01H BIT D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0
!CONTROL COMMAND TABLE a) Master Volume
Select Address 00H *VOL : Master Volume Attenuation level : +20 to -80dB(0.5dB/step), MUTE BIT D7 D6 D5 D4 VOL D3 D2 D1 D0
b) Balance
Select Address 01H BIT D7 CHS D6 D5 D4 BAL D3 D2 D1 D0
Don't Care
*CHS : Balance channel select "0" : Ach "Bch is attenuated" "1" : Bch "Ach is attenuated" *BAL : Ach and Bch Ach and Bch Balance Balance Level : 0 to -30dB (1dB/Step) , MUTE
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NJW1109
!CONTROL COMMAND TABLE a) Master Volume (Select Address: 00H)
Volume level : +20 to -80dB(0.5dB/step), MUTE
VOL
Gain(dB) 20 19.5 19 18.5 18 17.5 17 16.5 16 15.5 15 14.5 14 13.5 13 12.5 12 11.5 11 10.5 10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 5 4.5 4 3.5 3 -79.5 -80 Mute HEX FF FE FD FC FB FA F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 EF EE ED EC EB EA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 DF DE DD 38 37 00 D7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 D6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 D5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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NJW1109
b) Balance (Select Address: 01H)
Channel Setting (CHS) Attenuated Bch Gain Attenuated Ach Gain
Balance level : 0 to -30dB(1dB/step), MUTE
D7 0 1 BAL D4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Gain(dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 MUTE
D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
D3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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NJW1109
[CAUTION] The specifications on this data book are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this data book are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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